Our research focus on the ultra-low power and high performance FETs based on novel device structures and alternative channel materials. Tunneling FET and Negative capacitance FET are investigated with steep switching properties. High mobility materials (III-V compounds), high-K dielectric, and multi-gate structures are developed for better device performance.

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One of our research topics focus on the ultra-low-power and high performance devices. Following the tread of Moore’s law, the number of transistors in a dense integrated circuit doubles approximately every two years over the history of computing hardware. The continuous and aggressive scaling of MOSFET could improve the performance of CMOS technology. However, the required improvement in device parameters (current density, intrinsic delay, switching speed, leakage…) could no longer be satisfied by scaling the conventional Si technology. With the device size scales down, short channel effects such as “VT roll-off”, “punch-through”, and “drain induced barrier lowering (DIBL)” become severe. This leads to a weak gate control and high OFF-state leakage current. The decrease of device size and increase of packing density causes high power consumption issue as well. Several promising approaches are proposed to overcome the technological bottlenecks in order to continue the trend of performance scaling predicted by the Moore’s Law.

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One approach is increasing the electrostatic gate control by replacing the traditional planar MOSFET with multi-gate architectures and increasing the capacitive coupling between the gate and channel by using high-K gate dielectrics. Double-gate MOSFETs, Nanowire MOSFETs, FinFETs et al. are investigated to suppress the short channel effect.

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Another approach is enhancing the channel mobility by using alternative channel materials. Innovative modification of properties of traditional materials through strain engineering or deployment of new materials, such as III-V compound semiconductors, can increase the carrier injection velocity and density of states to obtain a better ON-state performance.

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The third approach is developing novel device structures which can obtain steep switching characteristics. Several device structures (tunneling FET and negative capacitance FET) are proposed to overcome the fundamental limits of Boltzmann transport to obtain steep subthreshold swing (SS) and maintain high ON/OFF ratio for achieving low power operation.

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Tunneling FET makes use of the band-to-band tunneling (BTBT) mechanism to get a steep SS. At OFF-state, the tunneling range of the device is large enough which makes the carriers at source side difficult tunnel to the channel. The small leakage current can be obtained with low gate bias. When gate bias increases, tunneling range of the device is reduced for carriers to go through with BTBT. The current can be large enough with high gate bias to achieve ON-state. Without the limit of Boltzmann distribution, SS smaller than 60 mV/decade at room temperature can be achieve with TFET structures.